|
The EDA Consortium Honors Sanyo With Design Achievement Award for Digital Camera Design, Sanyo Cites Celestry for Providing Clock Management, Signal Integrity and Timing Closure Tools
LAS VEGAS--(BUSINESS WIRE)--June 18, 2001--DESIGN AUTOMATION
CONFERENCE--The EDA Consortium today honored SANYO Electric Co., Ltd.
(Osaka, Japan) with its annual Design Achievement Award for its design
of a breakthrough digital camera system-on-chip (SoC). Accepting the
award, SANYO Microelectronics Research Center called particular
attention to EDA tools from Celestry Design Technologies, Inc. (San
Jose, California), a provider of Silicon Accurate Sign-off(TM)
physical analysis solutions for the semiconductor and electronics
industry, that enabled SANYO to reduce the time required to complete
the 8.5 million transistor, mixed-signal design.
``In order to meet time-to-market goals for this digital camera SoC
there were three key EDA technologies that were critical: clock
management, signal integrity and timing closure,'' said an official
from SANYO's Microelectronics Research Center.
SANYO's remarkable camera SoC impressed the judges with its mix of
sophisticated features and highly advanced degree of technical
sophistication and silicon integration. Able to store 120 minutes of
15fps video recording, or 12,000 still pictures, the chip also
includes a USB connection for simple, fast connectivity options. This
camera is a world wide first to have all of these features integrated
into a single System on Chip (SoC).
According to Dale A. Pollek, vice president of marketing at
Celestry, ``Power consumption is the most important issue facing
designers of mobile applications like the SANYO digital camera SoC.
Celestry's ClockWise(TM), the first clock synthesis solution
utilizing clock skew helps minimize power while optimizing timing,
allowed the SANYO design team to implement more than 50-gated clock
signals within an hour - a task that would have taken more than two
weeks with traditional clock tree synthesis. Additionally, the
estimated clock delay reported by ClockWise was incredibly close to
the final results.''
ClockWise's superior technology helped SANYO to reduce the power
consumption and clock design time with a plug-and-play interface into
existing place and route environments.
Signal integrity is a very important issue for 0.2 micron and
below processes according to the SANYO Microelectronics Research
Center. Celestry's Nautilus(TM) family (Nautilus-RC) provided very
accurate parasitic RC extraction including coupled capacitance that is
critical for coupling analysis. Also praised by the SANYO designers
were Nautilus-DC (formerly Millennium DC) that delivered precise
timing delay calculations and Nautilus-SI, the industry's first
full-chip signal integrity verification solution for multi-million
cells designs. Nautilus-SI captured the coupling effects on timing and
identified signal integrity problems due to coupling noise. Built on
top of Nautilus-SI, Nautilus-VT provided IR-drop information. These
tools provided an accurate SDF file for final timing analysis to
ensure Silicon Accurate Sign-off.
SANYO Microelectronics Research Center added, ``With Celestry's
ClockWise and Nautilus family of products as the cornerstone for
physical synthesis and physical analysis we were able to complete the
design project in only three months with two months for system design
and one month for physical implementation. In previous less complex
designs, we spent at least three months on layout and timing closure
alone.''
About Celestry's ClockWise and Useful-skew Methodology
Designed to avoid potential timing problems, ClockWise helps
designers rapidly achieve timing closure without replacing placement
and routing tools. Traditional physical design tools separate clock
design from other design tasks and simply minimize clock skew. In
contrast, ClockWise combines clock timing with data-path timing and
makes clock skew a useful tool to improve the performance and timing
robustness of a chip. Useful skew adjusts the effective timing
constraints on data-paths. Designers can reduce the number of design
iterations and quickly achieve timing closure by focusing on one
signal -- the clock.
About Celestry's Nautilus Product Family
Nautilus is the industry's first and most complete full-chip,
signal integrity verification solution for multi-million cell designs
and now includes Nautilus-VT. The Nautilus family of products offers
cell and transistor parameter and parasitic extraction, RC reduction,
delay calculation, IR-drop (voltage) and electromigration analysis.
Nautilus fits in with all the current cell-based design flows, such as
Place & Route tools, and can be used for high-end ASICs, COT, ASSP and
microprocessor designs.
About SANYO Electric Co., Ltd.
SANYO Electric Co., Ltd. is a global leader in multimedia & mobile
communications. The company's businesses cover a broad range of
multimedia & information systems, home appliances, commercial
equipment, electronic devices, batteries and other products. SANYO's
net sales in fiscal 2000, ended in March 31, 2001, amounted to 2,157.3
billion yen. The SANYO Group is truly an international organization,
comprising 85 manufacturing companies, 33 sales companies, and 38
affiliated companies based in 28 countries. For more information about
SANYO Electric Co., Ltd., visit www.sanyo.co.jp or e-mail
tokyo-pr@svnet.sanyo.co.jp.
About Celestry
Celestry is the leading provider of design solutions that enable
IC and SoC designers to achieve optimal performance from semiconductor
process technologies-solutions that help close the gap between
potential nanometer technology performance and the performance of ICs
and Sacs. The Company delivers a comprehensive suite of modeling,
simulation, physical analysis and physical synthesis tools and
services for developing digital, mixed-signal and analog ICs and Sacs
that are used in networking, communication, multimedia and computing
products. For more information visit www.celestry.com or email
info@celestry.com.
Notes to editors
Acronyms and definitions:
ASIC: Application Specific IC
ASSP: Application Specific Standard Product
COT: Customer Owned Tooling
DC: Delay Calculator
EDA: Electronic Design Automation
fps: Frames Per Second
IC: Integrated Circuit
IR: Voltage is the sum of current (I) and resistance (R)
IR Drop: Voltage Drop (as in the power lost due to resistance in
the interconnect)
RC: Resistance and Capacitance, mostly refers to parasitic R's
and C's in IC interconnect
SDF: Standard Delay Format, industry standard delay data exchange
file format
SI: Signal Integrity
SoC: System on Chip
USB: Universal Serial Bus
VT: Voltage
Nautilus, Nautilus-VT, Nautilus-RC, Celestry, ClockWise and
Silicon Accurate Sign-off are trademarks of Celestry Design
Technologies, Inc. All other trademarks are the property of their
respective owners.
Keywords -- ASIC, EDA,semiconductor, computer hardware, computers,
networking, software, telecom, embedded
Contact:
ValleyPR for Celestry
Georgia Marszalek, 650/345-7477
georgia@valleypr.com
|
|
CaféTalk |
